1. Field of the Invention
The present invention discloses a voltage controlling circuit, and more particularly, a voltage controlling circuit for clamping a voltage level of an amplifying signal within a predetermined range so as to restrain peaks.
2. Description of the Prior Art
Please refer to FIG. 1, which is a block diagram of a conventional analog circuit 100. The analog circuit 100 includes a gain amplifying module 110 and a gain controlling module 120. The gain amplifying module 110 is configured to amplify a gain of an input signal, such as an analog signal, so as to generate an amplifying signal. The gain controlling module 120 is configured to control a gain of the amplifying signal according to an external selection signal so as to generate an output signal, for example, generating the output signal by increasing or decreasing the gain of the amplifying signal by different multiples. The analog circuit 100 shown in FIG. 1 amplifies the input signal previously having an extremely-low voltage level with the aid of the gain amplifying module 110 so that the input signal is easier to process. The purpose of the gain controlling module 120 is to re-adjust the gain of the input signal according to different requirements indicated by the selection signal so as to generate the output signal meeting the selected requirement. However, in the design of the analog circuit 100, because of the over-high or over-low voltage level of the amplifying signal generated by the gain amplifying circuit 110, the voltage level of the output signal generated by the gain controlling circuit 120 is also over-high or over-low so that unexpected peaks occur, and precision of the output signal is reduced as a result.
Please refer to FIG. 2, which illustrates the analog circuit 100 shown in FIG. 1 in detail when being utilized for implementing an audio circuit. As shown in FIG. 2, the input signal may be an audio signal. The gain amplifying module 110 includes a first operational amplifier 112 and a variable resistor 114. The gain controlling module 120 includes a capacitor C1, a variable resistor 124, and a second operational amplifier 122. The first operational amplifier 112 and the variable resistor 114 are utilized for amplifying an audio gain of the input signal and for controlling the audio gain within a predetermined range so as to generate the amplifying signal. A high-pass filter is formed by the capacitor C1 and the variable resistor 124 so as to control the gain of the amplifying signal, and the output signal is generated by amplifying the controlled gain of the amplifying signal with the aid of the second operational amplifier 122. The output signal is then transmitted to a rear speaker for audio signal transmission, where resistance of the variable resistor 124 is controlled according to the selection signal. The variable resistor 124 may be combined with a plurality of switches, such as a plurality of transistors, so as to control the gain of the amplifying signal corresponding to different switch states of the plurality of switches determined by the selection signal.
Please refer to FIG. 3, which illustrates an implementation of the variable resistor 124 shown in FIG. 2. As shown in FIG. 3, the variable resistor 124 includes an N-type metal-oxide semiconductor field effect transistor (MOSFET) 124N and a P-type MOSFET 124P connected in parallel. Because of properties of both the N-type MOSFET 124N and the P-type MOSFET 124P, a parasitic bipolar junction transistor (BJT) 126N is formed on the N-type MOSFET 124N, and a parasitic BJT 126P is formed on the P-type MOSFET 124P. When a voltage level at a node LV1, which is located between the capacitor C1 and the variable resistor 124 shown in FIG. 2, is over-high due to the operational amplifier 112 charging the capacitor C1 so that the parasitic BJT 126P is switched on, a voltage level at a node LV2 is also over-high so that high-voltage peaks occur on the output signal Vout. Similarly, when the voltage level at the node LV1 is over-low since the voltage at the node LV1 is over-discharged, the voltage level at the node LV2 is also over-low so that low-voltage peaks occur on the output signal Vout as a result. Please refer to FIG. 4, which illustrates voltage levels at certain nodes of the analog circuit 100 shown in FIG. 2. As shown in FIG. 4, the voltage level at the node LG0 indicating the voltage level of the amplifying signal is in the form of a square wave. When the voltage level at the node LG0 is over-high, an obvious upward peak occurs at the node LV1 and at a front edge of the waveform of the output signal Vout. On the contrary, when the voltage level at the node LG0 is over-low, an obvious downward peak also occurs at the node LV1 and a rear edge of the waveform of the output voltage Vout.
The peaks occurring at the output signal Vout will significantly affect the precision of processing the output signal Vout and introduce noise. When the input signal is an audio signal, the peaks occurring at the output signal Vout will introduce significant noise when the speaker releases audio so that quality of the released audio is defective.